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ASAHI KASEI
[AK4103A]
AK4103A
192kHz 24-Bit DIT
GENERAL DESCRIPTION The AK4103A is a digital audio transmitter (DIT) which supports data rate up to 192kHz sample rate operation. The AK4103A supports AES3, IEC60958, S/PDIF & EIAJ CP1201 interface standards. The AK4103A accepts audio data, auxiliary information data and etc, which is then biphase-encoded and driven on to a cable. The audio serial port supports eight formats. FEATURES
o Sampling Rate up to 192kHz o Support AES3, IEC60958, S/PDIF & EIAJ CP1201 professional and consumer formats o Generates CRCC codes and parity bits o On-chip RS422 line driver o 16-byte on-chip buffer memory for Channel Status and User bits o Supports synchronous/asynchronous access to Channel Status and User bits o Supports multiple clock frequencies: 128fs, 256fs, 384fs and 512fs o Supports Left/Right justified and I2S audio formats o Easy to use 4 wire, Serial Host Interface o Audio Routing Mode (Transparent Mode) o Power supply: 4.75 to 5.25V o TTL level I/F o Small Package: 24pin VSOP o Temperature range of - 40 to 85 C
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ASAHI KASEI
[AK4103A]
n Block Diagram
TRANS Drivers DIF1 Drivers DIF0 Drivers Drivers CKS0 Drivers Drivers TXP TXN MCLK CKS1
DIF2
BICK LRCK SDTI Audio Serial Interface
Prescaler
C1 U1 V1 Register Biphase Encoder
FS0 FS1 FS2 FS3 Host Serial Interface CRCC Generator
MUX
CDTI
CDTO
CCLK
CSN
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PDN
ANS
RS422 Line Driver
VDD
VSS
BLS
2003/07
ASAHI KASEI
[AK4103A]
n Ordering Guide
AK4103AVF -40 +85C 24pin VSOP (0.65mm pitch)
n Pin Layout
V1 TRANS PDN MCLK SDTI BICK LRCK FS0/CSN FS1/CDTI FS2/CCLK FS3/CDTO C1
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20
U1 DIF2 DIF1 DIF0 TXP TXN VSS VDD CKS1 CKS0 BLS ANS
Top View
19 18 17 16 15 14 13
n Comparison AK4103 with AK4103A
Function Ambient Temperature CRCC generation by FS3-0 pins CRCC generation by FS3-0 bits AK4103 -10 ~ 70C Synchronous mode X Asynchronous mode X O: Input data is reflected to CRCC. X: Input data is ignored for CRCC. AK4103A -40 ~ 85C O O
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ASAHI KASEI
[AK4103A]
PIN/FUNCTION
No. 1 2 3 Pin Name V1 TRANS PDN I/O I I I Description Validity Bit Input Pin Audio Routing Mode (Transparent Mode) Pin at Synchronous mode 0: Normal mode, 1: Audio routing mode (transparent mode) Power Down & Reset Pin (Pull-up Pin) When "L", the AK4103A is powered-down, TXP/N pins are "L" and the control registers are reset to default values. Master Clock Input Pin Audio Serial Data Input Pin Audio Serial Data Clock Input/Output Pin Serial Clock for SDTI pin which can be configured as an output based on the DIF2-0 inputs. Input/Output Channel Clock Pin Indicates left or right channel, and can be configured as an output based on the DIF2-0 inputs. Sampling Frequency Select 0 Pin at Synchronous mode (Pull-down Pin) Host Interface Chip Select Pin at Asynchronous mode (Pull-down Pin) AK4112B Mode Pin at Audio routing mode (Pull-down Pin) 0: Non-AKM receivers mode, 1: AK4112B mode Sampling Frequency Select 1 Pin at Synchronous mode (Pull-down Pin) Host Interface Data Input Pin at Asynchronous mode (Pull-down Pin) Sampling Frequency Select 2 Pin at Synchronous mode (Pull-down Pin) Host Interface Bit Clock Input Pin at Asynchronous mode (Pull-down Pin) Sampling Frequency Select 3 Pin at Synchronous mode (Pull-down Pin) Host Interface Data Output Pin at Asynchronous mode (Pull-down Pin) Channel Status Bit Input Pin Asynchronous/Synchronous Mode Select Pin (Pull-up Pin) 0: Asynchronous mode, 1: Synchronous mode Block Start Input/Output Pin (Pull-down Pin) In normal mode, the channel status block output is "H" for the first four bytes. In audio routing mode, the pin is configured as an input. When PDN pin = "L", BLS pin goes "H" at Normal mode. Clock Mode Select 0 Pin (Pull-up Pin) Clock Mode Select 1 Pin (Pull-down Pin) Power Supply Pin, 4.75V5.25V Ground Pin, 0V Negative Differential Output Pin Positive Differential Output Pin Audio Serial Interface Select 0 Pin (Pull-down Pin) Audio Serial Interface Select 1 Pin (Pull-down Pin) Audio Serial Interface Select 2 Pin (Pull-down Pin) User Data Bit Input Pin for Channel 1 (Pull-down Pin)
4 5 6
MCLK SDTI BICK
I I I/O
7
LRCK
I/O
8
FS0 CSN AKMODE FS1 CDTI FS2 CCLK FS3 CDTO C1 ANS BLS
I I I I I I I I O I I I/O
9 10 11 12 13 14
15 CKS0 I 16 CKS1 I 17 VDD 18 VSS 19 TXN O 20 TXP O 21 DIF0 I 22 DIF1 I 23 DIF2 I 24 U1 I Notes: 1. Internal pull-up and pull-down resistors are connected on-chip. The value of the resistors is 43k (typ). 2. All input pins except internal pull-down/pull-up pins should not be left floating.
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ASAHI KASEI
[AK4103A]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 3) Parameter Power Supply Input Current (All pins except supply pins) Input Voltage Ambient Operating Temperature Storage Temperature Notes: 3. All voltages with respect to ground. Symbol VDD IIN VIND Ta Tstg min -0.3 -0.3 -40 -65 max 6.0 10 VDD+0.3 85 150 Units V mA V C C
WARNING: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1) Parameter Power Supply Symbol VDD min 4.75 typ 5.0 max 5.25 Units V
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
DC CHARACTERISTICS
(Ta=25C; VDD=4.75~5.25V) Parameter Symbol min typ max Units Power Supply Current (fs=108kHz, Note 4) IDD 6 15 mA High-Level Input Voltage VIH 2.4 V Low-Level Input Voltage VIL 0.8 V High-Level Output Voltage (Except TXP/N pins: Iout=-400A) VOH VDD-1.0 V (TXP/N pins: Iout= -8mA) VOH VDD-0.8 V Low-Level Output Voltage (Except TXP/N pins: Iout= 400A) VOL 0.4 V (TXP/N pins: Iout= 8mA) VOL 0.6 V Input Leakage Current Iin 10 A Notes: 4. Power supply current (IDD) is 3mA(typ)@fs=48kHz and 9mA(typ)@fs=192kHz. IDD increases by 20mA(typ) with professional output driver circuit. IDD is 350A(typ) if PDN pin = "L", TRANS pin = "H" and all other input pins except internal pull-up/pull-down pins are held to VSS.
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ASAHI KASEI
[AK4103A]
SWITCHING CHARACTERISTICS
(Ta=25C; VDD=4.75~5.25V; CL=20pF) Parameter Symbol min Master Clock Timing 3.584 fCLK Frequency Duty Cycle 40 dCLK LRCK Timing Frequency 28 fs Duty Cycle at Slave Mode 45 dLCK Duty Cycle at Master Mode Audio Interface Timing Slave Mode BICK Period 36 tBCK BICK Pulse Width Low 15 tBCKL Pulse Width High 15 tBCKH 15 tLRB LRCK Edge to BICK "" (Note 5) 15 tBLR BICK "" to LRCK Edge (Note 5) 8 tSDH SDTI Hold Time 8 tSDS SDTI Setup Time Master Mode BICK Frequency fBCK BICK Duty dBCK tMBLR -20 BICK "" to LRCK tSDH 20 SDTI Hold Time tSDS 20 SDTI Setup Time Control Interface Timing CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 50 CDTI Hold Time tCDH 50 CSN "H" Time tCSW 520 tCSS 50 CSN "" to CCLK "" tCSH 50 CCLK "" to CSN "" tDCD CDTO Delay tCCZ CSN "" to CDTO Hi-Z (Note 6) Power-down & Reset Timing PDN Pulse Width tPDW 150 Notes: 5. BICK rising edge must not occur at the same time as LRCK edge. 6. CDTO pin is internally connected to a pull-down resistor. typ max 27.648 60 192 55 50 Units MHz % kHz % %
ns ns ns ns ns ns ns 64fs 50 20 Hz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns
45 70
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ASAHI KASEI
[AK4103A]
n Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL dCLK = tCLKH x fCLK x 100 = tCLKL x fCLK x 100
MCLK
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Clock Timing
VIH VIL tBLR tLRB VIH VIL tSDS tSDH VIH VIL
LRCK
BICK
SDTI
Audio Interface Timing (Slave Mode)
LRCK
50%VDD
tMBLR BICK 50%VDD
tSDS
tSDH VIH VIL
SDTI
Audio Interface Timing (Master Mode)
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ASAHI KASEI
[AK4103A]
VIH CSN tCSS tCCKL tCCKH CCLK tCDH VIH VIL tCDS VIL
CDTI
C1
C0
*
*
VIH VIL
CDTO
Hi-Z (with pull-down resistor)
WRITE/READ Command Input Timing
tCSW VIH CSN tCSH VIH VIL VIL
CCLK
CDTI
D3
D2
D1
D0
VIH VIL Hi-Z (with pull-down resistor)
CDTO
WRITE Data Input Timing
VIH CSN VIL
CCLK
VIH VIL
CDTI
A1
A0
VIH VIL tDCD
CDTO
Hi-Z (with pull-down resistor)
D7
D6
D5
50%VDD
READ Data Output Timing 1
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ASAHI KASEI
tCSW CSN VIH VIL tCSH CCLK VIH VIL
[AK4103A]
CDTI
VIH VIL tCCZ
CDTO
D3
D2
D1
D0
50%VDD
READ Data Output Timing 2
tPDW PDN
VIL
Power-down & Reset Timing
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ASAHI KASEI
[AK4103A]
OPERATION OVERVIEW n General Description
The AK4103A is a monolithic CMOS circuit that biphase-encodes and transmits audio data, auxiliary information data and etc according to the AES3, IEC60958, S/PDIF and EIAJ CP1201 interface standards. There is one set of stereo channels that can be transmitted simultaneously. The chip accepts audio data and auxiliary information data separately, biphase-mark encodes the data internally, and drives it directly or through a transformer to a transmission line. There are two modes of operation: asynchronous and synchronous. See section of "Asynchronous mode / Synchronous mode".
n Initialization
The AK4103A takes 8 bit clock cycles to initialize after PDN pin goes inactive. Also, for correct synchronization, MCLK should be synchronized with LRCK but the phase is not critical.
n MCLK and LRCK Relationship
For correct synchronization, MCLK and LRCK should be derived from the same clock signal either directly (as through a frequency divider) or indirectly (for example, as through a DSP). The relationship of BICK to LRCK is fixed and should not change. If MCLK or LRCK move such that they are shifted (128fs x 3) or more MCLK cycles from their initial conditions, the chip will reset the internal frame and bit counters. However, control registers are not initialized. The following frequencies are supported for MCLK. CKS1 0 0 1 1 CKS0 0 1 0 1 MCLK 128fs 256fs 384fs 512fs fs 28k-192kHz 28k-108kHz 28k-54kHz 28k-54kHz
Table 1. MCLK Frequency
n Asynchronous Mode/ Synchronous Mode
1. Asynchronous Mode (software controlled) The AK4103A can be configured in the asynchronous mode by connecting the ANS pin to logic "L". In this mode the 16 to 24-bit audio samples are accepted through a configured audio serial port, and the channel status and user data through a serial control host interface (SCI). The SCI allows access to internal buffer memory and control registers which are used to store the channel status and user data. 4bytes per channel of user and channel status is stored. This data is multiplexed with the audio data from the audio serial port, the parity bit is generated, and the bit stream is biphase-mark encoded and driven through the RS422 line driver. The CRCC code for the channel status is also generated according to the professional mode definition in the AES3 standards. This mode also allows for software control for mute, reset, audio format selection, clock frequency settings and output enables, via the serial host interface.
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ASAHI KASEI
[AK4103A]
2. Synchronous Mode (hardware controlled) The AK4103A when configured in synchronous mode accepts 16 - 24 bit audio samples through the audio serial port and provides dedicated pins for the control data and allows all channel status, user data and validity bits to be serially input through port pins. This data is multiplexed, the parity bit generated, and the bit stream is biphase-mark encoded and driven through an RS422 line driver. 2-1. Audio Routing Mode (Transparent Mode) The AK4103A can be configured in audio routing mode (transparent mode) by ANS pin = TRANS pin = "1". In this mode, the channel status(C), user data(U) and validity(V) bits must pass through unaltered. The Block Start(B) signal is configured as an input, allowing the transmit block structure to be slaved to the block structure of the receiver. The C, U and V are now transmitted with the current audio sample. In audio routing mode, no CRCC bytes are generated and C bits pass through unaltered. In audio routing mode, the FS0/CSN pin changes definition to AKMODE pin. When set "H" the AK4103A can be configured directly with the AK4112B receiver. When set "L", it may be used with other nonAKM receivers. Setting the part with TRANS pin = "1" and ANS pin = "0" is illegal and places the chip into a test mode. Pin TRANS 0 1 0 1 Modes Synchronous/Asynchronous Asynchronous mode Source for C, U and V bits C Pin ORed Control Register U Pin ORed Control Register V Pin ORed Control Register C,U and V pin
ANS 0 0 1 1
Audio Routing Normal mode (Test mode) Normal mode Audio routing mode
Synchronous mode
Table 2. Mode setting
BLS
C (or U,V)
C(R191)
C(L0)
C(R0)
C(L1)
C(L31)
C(R31) C(L32)
LRCK 2 (except I S) LRCK 2 (I S) SDTI R191 L0 R0 L1 L31 R31 L32
Figure 1. Audio routing mode timing (AKMODE pin = "0")
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ASAHI KASEI
[AK4103A]
BLS
C (or U,V)
C(R191)
C(L0)
C(R0)
C(L1)
C(L31)
C(R31) C(L32)
LRCK SDTI 2 (except I S) SDTI 2 (I S)
R190
L191
R191
L0
L30
R30
L31
L191
R191
L0
R0
R30
L31
R31
Figure 2. Audio routing mode timing (AKMODE pin = "1")
n Block Start Timing
Normal mode In normal mode (TRANS pin = "0"), the block start signal is an output. It goes "H" two bit cycle after the beginning of channel 2 of frame 0 in each block, and stays "H" for the first 32 frames. Audio Routing Mode (Transparent Mode) In audio routing mode (transparent mode) (ANS pin = TRANS pin = "1"), the block start becomes an input. Except in I2S mode, a block start signal sampled any time from the first positive BICK edge of the previous left channel to the positive BICK edge preceding the transition of an LRCK indicating the left channel will result in the current left channel being taken as the first sub frame of the current block. See Figure 3 below.
LRCK 2 (except I S) LRCK 2 (I S) BICK (1) (n-1)th channel 1 nth channel 1
(n-1)th channel 1
nth channel 1
Figure 3. Block start timing in audio routing mode A block start signal arriving during "(1)" period will result in the usage of "nth channel 1" as the first sub-frame of the block.
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ASAHI KASEI
[AK4103A]
n C, U, V Serial Ports
Normal mode In normal mode (TRANS pin = "0"), the C, U and V bits are captured (either from the pins, in synchronous mode, or the control registers, in the asynchronous mode) in the sub frame following the audio data. The V bit is set to zero to indicate the audio data is suitable for conversion. See Figure 4 and Figure 5. Audio routing mode (transparent mode) In audio routing mode (transparent mode) (ANS pin = TRANS pin = "1"), the C, U and V bits are captured with the same sub-frame as the data to which the C, U and V bits correspond. In all DIF modes except 5 and 7, the C, U and V bits are captured at the first, rising edge of BICK after an LRCK transition. In modes 5 and 7 (I2S), the C, U and V bits are captured at the second rising edge. See Figure 6 and Figure 7.
LRCK BICK C,U,V
Channel1
Channel 2
Channel 1 C,U,V Previous Channel 2 C, U, V
Figure 4. Normal, DIF modes 0, 1, 2, 3, 4, and 6
LRCK BICK C,U,V
Channel 1
Channel 2
Channel 1 C, U, V Previous Channel 2 C, U, V
Figure 5. Normal, DIF modes 5 and 7 (I2S)
LRCK BICK C,U,V
Channel 1
Channel 2
Channel 1 C, U, V
Channel 2 C, U, V
Figure 6. Audio routing, DIF modes 0, 1, 2, 3, 4, and 6
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ASAHI KASEI
[AK4103A]
LRCK BICK C,U,V
Channel 1
Channel 2
Channel 1 C, U, V
Channel 2 C, U, V
Figure 7. Audio routing, DIF modes 5 and 7 (I2S)
n Audio Serial Interface
The audio serial interface is used to input audio data and consists of three pins: Bit Clock (BICK), Word Clock (LRCK) & Data pin (SDTI). LRCK indicates the particular channel, left or right. The DIF 2-0 pins in synchronous mode and control registers in asynchronous mode select the particular input mode. In asynchronous mode, DIF2-0 bits are logically ORed with DIF2-0 pins. Audio data format supports 16-24 bits, right justified and left justified modes. The I2S mode is also supported. The AK4103A can be configured in master and slave modes. Mode 0 1 2 3 4 5 6 7 DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIF0 0 1 0 1 0 1 0 1 SDTI 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S Master / Slave Slave Slave Slave Slave Slave Slave Master Master LRCK H/L (I) H/L (I) H/L (I) H/L (I) H/L (I) L/H (I) H/L (O) L/H (O) BICK 32fs-128fs (I) 36fs-128fs (I) 40fs-128fs (I) 48fs-128fs (I) 48fs-128fs (I) 50fs-128fs (I) 64fs (O) 64fs (O)
Table 3. Audio Data Format Modes [NOTE; (I): Input, (O): Output]
LRCK(i)
0 1 2 15 16 17 30 31 0 1 2 15 16 17 30 31 0 1
BICK(i)
15
14
1
0
15
14
1
0
SDTI(i)
15:MSB, 0:LSB Lch Data Rch Data
Figure 8. Mode 0 Timing
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ASAHI KASEI
[AK4103A]
LRCK(i)
0 1 2 13 14 15 30 31 0 1 2 13 14 15 30 31 0 1
BICK(i)
17
16
1
0
17
16
1
0
SDTI(i)
17:MSB, 0:LSB Lch Data Rch Data
Figure 9. Mode 1 Timing
LRCK(i)
0 1 2 11 12 13 30 31 0 1 2 11 12 13 30 31 0 1
BICK(i)
19
18
1
0
19
18
1
0
SDTI(i)
19:MSB, 0:LSB Lch Data Rch Data
Figure 10. Mode 2 Timing
LRCK(i)
0 1 8 9 10 11 30 31 0 1 8 9 10 11 30 31 0 1
BICK(i)
23
22
21
20
1
0
23
22
21
20
1
0
SDTI(i)
23:MSB, 0:LSB Lch Data Rch Data
Figure 11. Mode 3 Timing
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ASAHI KASEI
[AK4103A]
LRCK
0 1 2 21 22 23 30 31 0 1 2 21 22 23 30 31 0 1
BICK
23 22
21
2
1
0
23 22
21
2
1
0
23 22
SDTI(i)
23:MSB, 0:LSB Lch Data Rch Data
Figure 12. Mode 4, 6 Timing Mode 4: LRCK, BICK: Input Mode 6: LRCK, BICK: Output
LRCK
0 1 2 3 22 23 24 31 0 1 2 3 22 23 24 31 0 1
BICK
SDTI(i)
23
22 21
2
1
0
23 22
3
2
1
0
23
23:MSB, 0:LSB Lch Data Rch Data
Figure 13. Mode 5, 7 Timing Mode 5: LRCK, BICK: Input Mode 7: LRCK, BICK: Output
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ASAHI KASEI
[AK4103A]
n Sampling frequency setting
Bits 3-0 of Channel Status Byte 3 in consumer mode can be set by FS3-0 pins. Also bits 7-6 of Channel Status Byte 0 and bits 6-3 of Channel Status Byte 4 in professional mode can be set by FS3-0 pins. FS[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Sampling Frequency 44.1kHz Not Indicated 48kHz 32kHz 22.05kHz Reserved 24kHz Reserved 88.2kHz Reserved 96kHz Reserved 176.4kHz Reserved 192kHz Reserved Byte 3 Bits 3-0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Table 4. Sampling frequency setting (Consumer mode)
FS[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Sampling Frequency Not Defined 44.1kHz 48kHz 32kHz Not Defined Not Defined Not Defined Not Defined For vectoring 22.05kHz 88.2kHz 176.4kHz 192kHz 24kHz 96kHz Not Defined
Byte 0 Bits 7-6 00 01 10 11 00 00 00 00 00 00 00 00 00 00 00 00
Byte 4 Bits 6-3 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 0011 0001 0010 1111
Table 5. Sampling frequency setting (Professional mode)
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ASAHI KASEI
[AK4103A]
n Data Transmission Format
Data transmitted on the TX outputs is formatted in blocks as shown in Figure 14. Each block consists of 192 frames. A frame of data contains two sub-frames. A sub-frame consists of 32 bits of information. Each data bit received is coded using a bi-phase mark encoding as a two binary state symbol. The preambles violate bi-phase encoding so they may be differentiated from data. In bi-phase encoding, the first state of an input symbol is always the inverse of the last state of the previous data symbol. For a logic "0", the second state of the symbol is the same as the first state. For a "1", the second state is the opposite of the first. Figure 15 illustrates a sample stream of 8 data bits encoded in 16 symbol states.
M Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2 Sub-frame Frame 191 Sub-frame Frame 1
Frame 0 Figure 14. Block format
0
1
1
0
0
0
1
0
Figure 15. A biphase-encoded bit stream The sub-frame is defined in Figure 16 below. Bits 0-3 of the sub-frame represent a preamble for synchronization. There are three preambles. The block preamble, B, is contained in the first sub-frame of Frame 0. The channel 1 preamble, M, is contained in the first sub-frame of all other frames. The channel 2 preamble, W, is contained in all of the second subframes. Table 6 below defines the symbol encoding for each of the preambles. Bits 4-27 of the sub-frame contain the 24 bit audio sample in 2's complement format with bit 27 as the most significant bit. For 16 bit mode, Bits 4-11 are all 0. Bit 28 is the validity flag. This is "H" if the audio sample is unreliable. Bit 29 is a user data bit. Frame 0 contains the first bit of a 192 bit user data word. Frame 191 contains the last bit of the user data word. Bit 30 is a channel status bit. Again frame 0 contains the first bit of the 192 bit word with the last bit in frame 191. Bit 31 is an even parity bit for bits 4-31 of the sub-frame.
0
34 L Sync S B
Audio sample
Figure 16. Sub-frame format
27 28 29 30 31 M SVUCP B
The block of data contains consecutive frames transmitted at a state-bit rate of 64 times the sample frequency, fs. For stereophonic audio, the left or A channel data is in channel 1 while the right or B data is in channel 2. For monophonic audio, channel 1 contains the audio data. Preamble B M W Preceding state = 0 11101000 11100010 11100100 Preceding state = 1 00010111 00011101 00011011
Table 6. Sub-frame preamble encoding
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ASAHI KASEI
[AK4103A]
n Line Driver
There is an RS422 line driver on chip. The AES3 specification states that the line driver shall have a balanced output with an internal impedance of 110 ohms 20% and also requires a balanced output drive capability of 2 to 7 volts peakto-peak into 110 ohm load. The internal impedance of the RS422 driver along with a series resistors of 56 ohms realizes this requirement. For consumer use(S/PDIF), the specifications require an output impedance of 75 ohms 20% and a driver level of 0.520% volts peak to peak. A combination of 330 ohms in parallel with 100 ohms realizes this requirement. The outputs can be set to ground by resetting the device or a software mute. 56 TXP XLR Connector TXN Figure 17. Professional Output Driver Circuit 330 TXP 100 TXN Figure 18. Consumer Output Driver Circuit RCA Phono Connector 0.1u Transformer 0.1u Transformer
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ASAHI KASEI
[AK4103A]
n Serial Control Interface
In asynchronous mode, four of the dual function pins become CSN, CCLK, CDTI and CDTO, a 4 wire microprocessor interface. The internal 18 byte control register can then be read and written. The contents of the control register define, in part, the mode of operation for the AK4103A. Figure 19 illustrates the serial data flow associated with SCI read and write operations. C1-0 bits are the chip address. The AK4103A looks for C1-0 bits to be a "11" before responding to the incoming data. R/W is the Read/ Write bit which is "0" for a read operation and "1" for a write operation. The register address contained in A7-0 bits is decoded to select a particular byte of the control register. D7-0 bits on CDTI pin is the control data coming from the microprocessor during a write operation. D7-0 bits on CDTO pin is the contents of the addressed byte from the control register requested during a read operation. The address and data bits are framed by CSN pin = "0". During a write operation, each address and data bit is sampled on the rising edge of CCLK. During a read operation, the address bits are sampled on the rising edge of CCLK while data on CDTO is output on the falling edge of CCLK. CCLK has a maximum frequency of 5 MHz.
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CCLK
CDTI WRITE CDTO CDTI READ CDTO
C1 C0
*
*
*
*
*
R/W A7
A6
A5
A4
A3
A2
A1
A0 D7
D6
D5
D4 D3
D2 D1
D0
Hi-Z (with pull-down resistor)
"L"
A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1
C0
*
*
*
*
*
R/W A7
A6
Hi-Z (with pull-down resistor)
D7
D6
D5
D4 D3 D2
D1
D0
Hi-Z
C1-C0: R/W: *: A7-A0: D7-D0:
Chip Address (Fixed to "11") READ/WRITE (0:READ, 1:WRITE) Don't care Register Address Control Data
Figure 19. Control I/F Timing
AK4103A
CSN CCLK CDTI CDTO
P
CSN1 CCLK CDTI CDTO CSN2
AK4103A
CSN CCLK CDTI CDTO
Figure 20. Typical connection with P Note: External pull-up resistor should not be attached to CDTO pins since CDTO pin is internally connected to the pull-down resistor.
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ASAHI KASEI
[AK4103A]
n Register Map
Addr 00H 01H 02H 03H 04H 05H 06H09H 0AH0DH 0EH11H Register Name Clock/Format Control Validity/fs Control A-channel C-bit buffer for Byte 0 A-channel C-bit buffer for Byte 1 A-channel C-bit buffer for Byte 2 A-channel C-bit buffer for Byte 3 B-channel C-bit buffer for Byte 0-3 A-channel U-bit buffer for Byte 0-3 B-channel U-bit buffer for Byte 0-3 D7 CRCE 0 CA7 CA15 CA23 CA31 CB7 ... CB31 UA7 ... UA31 UB7 ... UB31 D6 DIF2 0 CA6 CA14 CA22 CA30 ... ... ... ... ... ... D5 DIF1 0 CA5 CA13 CA21 CA29 ... ... ... ... ... D4 DIF0 V1 CA4 CA12 CA20 CA28 ... ... ... ... ... D3 CKS1 FS3 CA3 CA11 CA19 CA27 ... ... ... ... ... ... D2 CKS0 FS2 CA2 CA10 CA18 CA26 ... ... ... ... ... ... D1 MUTEN FS1 CA1 CA9 CA17 CA25 ... ... ... ... ... ... D0 RSTN FS0 CA0 CA8 CA16 CA24 CB0 ... CB24 UA0 ... UA24 UB0 ... UB24
... ... Table 7. Register Map
Notes: (1) In stereo mode, A indicates Left Channel and B indicates Right Channel. (2) In asynchronous mode, the DIF2-0 and CKS1-0 bits are logically "ORed" with the DIF2-0 and CKS1-0 pins. (3) For addresses from 12H to FFH, data is not written. (4) The PDN pin = "L" resets the registers to their default values.
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ASAHI KASEI
[AK4103A]
n Register Definitions
Addr 00H
Register Name Clock/Format Control R/W Default
D7 CRCE R/W 1
D6 DIF2 R/W 0
D5 DIF1 R/W 0
D4 DIF0 R/W 0
D3 CKS1 R/W 0
D2 CKS0 R/W 0
D1 MUTEN R/W 1
D0 RSTN R/W 1
RSTN: Timing Reset. 0: Resets the internal frame and bit counters. Control registers are not initialized. TXP pin is "H" and TXN pin is "L". In normal mode, BLS pin is "H". 1: Normal operation. (Default) MUTEN: Power Down and Mute for Asynchronous Mode. 0: Power Down Command. Control registers are not initialized. TXP and TXN pins are "L". In normal mode, BLS pin is "H". 1: Normal operation. (Default) CKS1-0: Master Clock Frequency Select. (See Table 1.) Default: "00" (Mode 0: MCLK=128fs) CKS1-0 bits are logically ORed with CKS1-0 pins. DIF2-0: Audio Data Format. (See Table 3.) Default: "000" (Mode 0: 16bit right justified) DIF2-0 bits are logically ORed with DIF2-0 pins. CRCE: CRCC Enable at professional mode. 0: CRCC is not generated. 1: CRCC is generated at professional mode. In consumer mode, CRCC is not generated. (Default)
Addr 01H
Register Name Validity/fs Control R/W Default
D7 0 RD 0
D6 0 RD 0
D5 0 RD 0
D4 V1 R/W 0
D3 FS3 R/W 0
D2 FS2 R/W 0
D1 FS1 R/W 0
D0 FS0 R/W 0
FS3-0: Sampling Frequency Select. (See Table 4 and Table 5.) Default: "0000" ("44.1kHz" in consumer mode; "Not defined" in professional mode. ) V1: Validity Flag. 0: Valid (Default) 1: Invalid
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ASAHI KASEI
[AK4103A]
Addr 02H 06H
Register Name A-channel C-bit buffer for Byte 0 B-channel C-bit buffer for Byte 0 R/W Default C0-7: Channel Status Byte 0 Default: "00100000"
D7 CA7 CB7 R/W 0
D6 CA6 CB6 R/W 0
D5 CA5 CB5 R/W 0
D4 CA4 CB4 R/W 0
D3 CA3 CB3 R/W 0
D2 CA2 CB2 R/W 1
D1 CA1 CB1 R/W 0
D0 CA0 CB0 R/W 0
Addr 03H 07H
Register Name A-channel C-bit buffer for Byte 1 B-channel C-bit buffer for Byte 1 R/W Default
D7 CA15 CB15 R/W 0
D6 CA14 CB14 R/W 0
D5 CA13 CB13 R/W 0
D4 CA12 CB12 R/W 0
D3 CA11 CB11 R/W 0
D2 CA10 CB10 R/W 0
D1 CA9 CB9 R/W 0
D0 CA8 CB8 R/W 0
C8-15: Channel Status Byte 1 Default: "00000000"
Addr 04H
Register Name A-channel C-bit buffer for Byte 2 R/W Default
D7 CA23 R/W 0
D6 CA22 R/W 0
D5 CA21 R/W 0
D4 CA20 R/W 1
D3 CA19 R/W 0
D2 CA18 R/W 0
D1 CA17 R/W 0
D0 CA16 R/W 0
CA16-23: Channel Status Byte 2 for A-channel Default: "00001000"
Addr 08H
Register Name B-channel C-bit buffer for Byte 2 R/W Default
D7 CB23 R/W 0
D6 CB22 R/W 0
D5 CB21 R/W 1
D4 CB20 R/W 0
D3 CB19 R/W 0
D2 CB18 R/W 0
D1 CB17 R/W 0
D0 CB16 R/W 0
CB16-23: Channel Status Byte 2 for B-channel Default: "00000100"
Addr 05H 09H
Register Name A-channel C-bit buffer for Byte 3 B-channel C-bit buffer for Byte 3 R/W Default
D7 CA31 CB31 R/W 0
D6 CA30 CB30 R/W 0
D5 CA29 CB29 R/W 0
D4 CA28 CB28 R/W 0
D3 CA27 CB27 R/W 0
D2 CA26 CB26 R/W 0
D1 CA25 CB25 R/W 1
D0 CA24 CB24 R/W 0
C24-31: Channel Status Byte 3 Default: "01000000"
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ASAHI KASEI
[AK4103A]
Addr 0AH0DH 0EH11H
Register Name A-channel U-bit buffer for Byte 0-3 B-channel U-bit buffer for Byte 0-3 R/W Default U0-31: User Data Default: all "0"
D7 UA7 ... UA31 UB7 ... UB31 R/W 0
D6 ... ... ... ... R/W 0
D5 ... ... ... ... R/W 0
D4 ... ... ... ... R/W 0
D3 ... ... ... ... R/W 0
D2 ... ... ... ... R/W 0
D1 ... ... ... ... R/W 0
D0 UA0 ... UA24 UB0 ... UB24 R/W 0
n Default values of control registers
Bits CRCE DIF2-0 CKS1-0 V1 FS3-0 MUTEN RSTN Channel Status Byte0 - Bit0 - Bit1 - Bit2 - Bit3-5 - Bit6-7 Byte1 - Bit0-7 Byte2 - Bit0-3 - Bit4-7 Default 1 000 00 0 0000 1 1
CRCC is generated. 16bit, Right justified MCLK=128fs Valid data fs=44.1kHz Normal Operation Normal Operation
0 Consumer Mode 0 Audio Mode 1 No Copyright 000 No Emphasis 00 Mode 0 00000000 General Category Code 0000 Source Number: Don't care 1000 Channel A Source channel 0100 Channel B Source channel Byte3 - Bit0-3 0100 fs=48kHz - Bit4-5 00 Standard Clock Accuracy - Bit6-7 00 User Data All zeros Table 8. Default Values of Control Register
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ASAHI KASEI
[AK4103A]
PACKAGE
24pin VSOP (Unit: mm)
*7.80.15 1.250.2
24
13 A 7.60.2 0.150.05 0.10.1 Detail A 0-10 0.50.2 0.10
Epoxy Cu Solder plate (Pb free) 2003/07 - 25 -
1 0.220.1
12 0.65
Seating Plane
NOTE: Dimension "*" does not include mold flash.
n Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment:
MS0251-E-00
*5.60.2
ASAHI KASEI
[AK4103A]
MARKING
AKM AK4103AVF AAXXXX
Contents of AAXXXX AA: Lot# XXXX: Date Code
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
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2003/07

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